1. Field of the Invention
Embodiments of the invention generally relate to an apparatus and method for manufacturing a semiconductor device. More particularly, the invention is directed to an apparatus and method for thermally processing a substrate.
2. Description of the Related Art
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. One of the major steps the industry has taken to address these demands is to change from batch processing silicon substrates in large furnaces to single substrate processing in a small chamber.
During single substrate processing, the substrate is typically heated to a high temperature to allow various chemical and physical reactions to take place in multiple IC devices disposed within portions of the substrate. Of particular interest, favorable electrical performance of the IC devices requires implanted regions to be annealed. Annealing recreates a crystalline structure from regions of the substrate that were previously made amorphous, and activates dopants by incorporating their atoms into the crystalline lattice of the substrate.
Thermal annealing processes usually provide a relatively large amount of thermal energy to the substrate in a short amount of time, and then rapidly cool the substrate to terminate the thermal process. Examples of thermal annealing processes currently in use include rapid thermal processing (RTP) and impulse (spike) annealing. Conventional RTP processes heat the entire substrate even though the IC devices reside only in the upper surface of the silicon substrate. Therefore, the rate to heat and/or cool the substrate is limited by the size of the substrate. Moreover, once the entire substrate is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, RTP systems usually do not achieve a 400° C./s ramp-up rate or a 150° C./s ramp-down rate. While RTP and spike annealing processes are known, current processes ramp substrate temperatures too slowly during the thermal process and therefore exposes the substrate to elevated temperatures for an extended period of time. These thermal budget problems become more severe with increasing substrate sizes, increasing switching speeds, and/or decreasing feature sizes.
To resolve some of the problems raised in conventional RTP processes, various scanning laser anneal techniques have been used to anneal surfaces of substrates. In general, these techniques deliver a constant energy flux to a small region on the surface of a substrate while the substrate is translated, or scanned, relative to the energy delivered to the small region. Due to stringent uniformity requirements and the complexity of minimizing the overlap of scanned regions across the substrate surface, these types of processes are not effective for thermal processing contact level devices formed on the surface of the substrate.
Dynamic surface annealing (DSA) techniques have been developed to anneal finite regions on the surface of the substrate to provide well-defined annealed and/or re-melted regions on the surface of the substrate. Generally, during such laser anneal processes, various regions on the surface of the substrate are sequentially exposed to a desired amount of energy delivered from the laser to cause the preferential heating of desired regions of the substrate. These techniques are preferred over conventional processes that sweep the laser energy across the surface of the substrate because the overlap between adjacent scanned regions is strictly limited to the unused space between die, or kurf lines, resulting in more uniform annealing across the desired regions of the substrate.
One disadvantage to DSA techniques is that annealing a portion of the surface of the substrate subjects the interface region between annealed portions and non-annealed portions to high thermal stresses during annealing due to temperature differences of up to 500° C. In most cases, these thermal stresses are relieved as heat conducts from the annealed region into the non-annealed region of the substrate. However, as the annealing process moves toward an edge of the substrate, the availability of heat-absorbing substrate domains is reduced by proximity to the edge, and thermal stresses cause physical deformation or breakage of the substrate.
FIG. 1 illustrates an annealing process attempting to anneal a portion 102 of substrate 100 near edge 104 of substrate 100. The electromagnetic energy 106 radiating from source 108 heats portion 102, while edge portion 110 of substrate 100 remains unheated. The interface area between annealed portion 102 and edge portion 110 develops high thermal stress due to the relatively small heat-absorbing capacity of edge portion 110. This high thermal stress is frequently relieved by deformation or breakage in edge portion 110 near edge 104 of substrate 100. Thus, there is a need for a thermal processing apparatus and method capable of annealing any desired region of the substrate without damaging the substrate.